The integrated circuit has become indispensable in our daily life, including food, clothing, lodging, transportation, education, and entertainment. Product assembled using integrated circuit devices can be found everywhere. Sophisticated electronic products continue to be developed that are more user-friendly and have functions that are more complicated. In order to provide improving convenience and usage, product design trends are towards lighter, thinner, shorter, and smaller.
Higher integration can be achieved through chip scale package (CSP) applications such as flip chip technology. Flip chip technology can employ area arrays for bump pads including connections to a carrier, thereby reducing package area and shortening transmission paths. A flip chip is generally a semiconductor device, such as an integrated circuit, having bead-like terminals formed on one surface of the chip. The terminals serve to both secure the chip to a circuit board and electrically connect the flip chip's circuitry to a conductor pattern formed on the circuit board, which may be a ceramic substrate, printed wiring board, flexible circuit, or a silicon substrate. The typical flip chip is generally quite small, resulting in the terminals being crowded along the perimeter. As a result, conductor patterns are typically composed of numerous conductors often spaced closely.
Because of the fine patterns of the terminals and conductor pattern, soldering a flip chip to its conductor pattern requires a significant degree of precision. Reflow solder techniques are widely utilized in the soldering of flip chips. Such techniques typically involve forming solder bumps on the surface of the flip chip. Heating the solder above its melting temperature serves to form the characteristic solder bumps. The chip is then soldered to the conductor pattern by registering the solder bumps with their respective conductors, and reheating, or reflowing, the solder so as to metallurgically and electrically bond the chip to the conductor pattern.
Deposition and reflow of the solder must be precisely controlled not only to coincide with the spacing of the terminals and the size of the conductors, but also to control the height of the solder bumps after soldering. Controlling the height of solder bumps after reflow is necessary in order to provide proper positioning of the chip after reflow. Sufficient spacing between the chip and substrate is necessary for enabling stress relief during thermal cycles, providing electrical isolation, allowing cleaning solutions for removing undesirable residues during manufacturing, and enabling bonding and encapsulation materials between the chip and the substrate.
By properly limiting the degree to which the molten solder can laterally expand during reflow, the height of the solder bumps, and therefore the spacing between chip and substrate, can be closely controlled by depositing an appropriate amount of solder at each terminal location. Packaging processes are still plagued by conventional techniques that cannot closely control the height of a flip chip's solder bumps and suffer from excessive solder wetting, reduced collapse height, poor IC planarity, solder overflow and insufficient lead registration or locking.
Thus, a need still remains for an integrated circuit package system to provide improved package performance and manufacturing including control over solder bump reflow and package encapsulation. In view of the increasing demand for improved integrated circuits and particularly more functions in smaller products at lower costs, it is increasingly critical that answers be found to these problems.
Solutions to these problems have been long sought but prior developments have not taught or suggested any solutions and, thus, solutions to these problems have long eluded those skilled in the art.